1. Field of the Invention
This invention relates to interconnect circuitry for connecting a plurality of data sources to a plurality of data destinations. More particularly, this invention relates to the management of arbitration between a plurality of data sources seeking to access a data output.
2. Description of the Prior Art
It is known to provide interconnect circuitry, such as a crossbar circuit, that is a switch infrastructure for connecting multiple inputs to multiple outputs in a matrix manner. Crossbar circuitry can be used to interconnect a plurality of source circuits and a plurality of destination circuits such that data input to the crossbar circuitry from any of the plurality of source circuits can be output to any of the plurality of destination circuits. Crossbar circuits can be used in a variety of implementations. For example, in a data processing system implementation, such crossbar circuitry can be used to interconnect a plurality of processors used to perform data processing operations on data values with a plurality of memory devices used to store those data values, thereby allowing the data values from any memory device to be routed to any processor.
A problem with known crossbar circuits is they require a large area for the components required to form the crossbar circuitry and the significant number of control lines required for routing control signals to those components. Crossbar circuits may consume a disadvantageous amount of power. Furthermore, the complexity of crossbar circuits tends to grow rapidly with size, making many of the known techniques impractical for use with crossbar circuits required to interconnect a large number of source circuits with a large number of destination circuits. One particular problem with such crossbar circuits is how to efficiently support desired arbitration schemes.
It is known that it is desirable to provide arbitration mechanisms between data source circuits which compete to connect to a data destination circuit via interconnect circuitry. In some situations it may be acceptable to adopt a fixed priority scheme in which each data source circuit has a fixed priority value and when multiple data source circuits compete for access to a destination circuit, the data source circuit with the highest fixed priority value will be permitted the access. While it is possible to statically configure an interconnect circuit to reflect such a fixed priority, such a fixed priority arbitration scheme suffers from practical disadvantages. For example, with a fixed priority arbitration scheme, a high priority data source circuit may “starve” a lower priority data source circuit from any access to a data destination circuit. In order to deal with the limitations of fixed priority arbitration schemes, it is known to provide adaptive priority arbitration schemes in which the priority associated with each data source circuit can change with time depending upon the state of the system and the previous processing activity of the system. Examples of such adaptive priority arbitration schemes include a least recently granted scheme in which the highest priority is given to the data source circuit which has least recently been granted access to a data destination circuit. Another example is a round robin scheme in which the data source circuits take turns in being the highest priority within the arbitration scheme. Different adaptive priority arbitration schemes are desirable for use in different situations. It is desirable that interconnect circuitry should be able to support adaptive priority arbitration schemes.
A problem with supporting adaptive priority arbitration schemes in the context of crossbar circuitry is that the configuration of the crossbar circuitry to reflect the current priority levels is distributed through the crossbar circuitry such that the different portions of the crossbar circuitry may perform local arbitration control. This is desirable for improving the speed and parallelism of operation. However, when the adaptive priority changes due to processing operations performed, it is necessary to change this distributed configuration to reflect the updated priority levels. The present techniques are concerned with managing such adaptive priority schemes in an efficient and scalable manner for use within interconnect circuitry such as crossbar circuitry.